TC1796 Datasheet, PDF (107/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1796
2) Parameter test correlation for V_DDEBU = 2.5 V ± 5%
Electrical Parameters
4.3.3 Power Sequencing
There is a restriction for the power sequencing of the 3.3 V domain including V_DDEBU as
shown in Figure 29: it must always be higher than 1.5 V domain - 0.5 V. The grey area
shows the valid range for V_3.3V and V_DDEBU relative to an exemplary 1.5 V ramp.
V_DDP, V_DDOSC3, V_DDFL3, V_DDM, V_DDMF belong to the 3.3 V power supply domain, that is
referenced in Figure 29 as V_3.3. The V_DDM and V_DDMF sub domains are connected with
anti parallel ESD protection diodes in TC1796 design steps BC and BD. The V_DDM,
V_DDMF, V_DDP, V_DDOSC3 sub domains are connected with anti parallel ESD protection
diodes in TC1796 design step BE.
V_DD, V_DDOSC and V_DDAF belong to the 1.5 V power supply domain, referenced as V_1.5.
V_DDEBU belongs to its own 2.5V to 3.3V domain.
3.3V
1.5V
V_3.3, V_DDEBU
V_1.5
V_DDP
(3.3V)
PORST
V_3.3, V_DDEBU > V_1.5 - 0.5V
Time
Time
PowerSeq 2
Figure 29 V_DDP / V_DDEBU / V_DD Power Up Sequence
All ground pins V_SS must be externally connected to one single star point in the system.
The difference voltage between the ground pins must not exceed 200 mV.
The PORST signal must be activated at latest before any power supply voltage falls
below the levels shown on the figure below. In this case, only the memory row of a Flash
memory that was a target of a write at the moment of the power loss will contain
unreliable content. Additionally, the PORST signal should be activated as soon as
possible. The sooner the PORST signal is activated, the less time the system operates
outside of the normal operating power supply range.
Data Sheet
107
V1.0, 2008-04