TC1796 Datasheet, PDF (114/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1796
Electrical Parameters
±4.0
D_P ns
±3.5
f_CPU = 50 MHz (K = 8)
f_CPU = 50 MHz (K = 14)
±3.0
±2.5
±2.0
f_CPU = 100 MHz (K = 4)
f_CPU = 100 MHz (K = 7)
±1.5
±1.0
f_CPU = 150 MHz (K = 4)
±0.5
±0.0
0
2
4
6
8
10
12
14
16
18
20
D_P = Max. jitter
P = Number of consecutive f_CPU periods
K = K-divider of PLL
P
TC1976_PLL_DETAIL
Figure 33
Approximated Maximum Accumulated PLL Jitter for Typical CPU
Clock Frequencies f_CPU (detail)
Note: The specified PLL jitter values are valid if the capacitive load at the External Bus
Unit (EBU) is limited to C_L=20pF.
Note: The maximum peak-to-peak noise on the Core Supply Voltage (measured
between V_DD at pin E23 and V_SS at pin D23, or adjacent supply pairs) is limited to
a peak-to-peak voltage of V_PP = 30mV. This condition can be achieved by
appropriate blocking of the Core Supply Voltage as near as possible to the supply
pins and using PCB supply and ground planes.=20pF.
Data Sheet
114
V1.0, 2008-04