TC1796 Datasheet, PDF (39/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1796
Functional Description
3.3
Architectural Address Map
Table 5 shows the overall architectural address map as defined for the TriCore and
implemented in TC1796.
Table 5
TC1796 Architectural Address Map
Seg- Contents
ment
Size
Description
0-7 Global
8 × 256
Mbyte
Reserved (MMU space), cached
8
Global
Memory
256 Mbyte EBU (246 Mbyte), PMU with PFLASH, DFLASH,
BROM, memory reserved for Emulation, cached
9
Global
Memory
256 Mbyte FPI space; cached
10 Global
Memory
256 Mbyte EBU (246 Mbyte), PMU with PFLASH, DFLASH,
BROM, memory reserved for Emulation, non-
cached
11 Global
Memory
256 Mbyte FPI space; non-cached
12 Local LMB 256 Mbyte DMU, bottom 4 Mbyte visible from FPI Bus in
Memory
segment 14, cached
13 DMI
64 Mbyte Local Data Memory RAM, non-cached
PMI
64 Mbyte Local Code Memory RAM, non-cached
EXTPER
96 Mbyte External Peripheral Space, non-cached
EXTEMU 16 Mbyte External Emulator Range, non-cached
BOOTROM 16 Mbyte Boot ROM space, BROM mirror; non-cached
14 EXTPER
128 Mbyte External Peripheral Space non-speculative, no
execution, non-cached
CPU[0 ..15] 16 × 8
image region Mbyte
Non-speculative, no execution, non-cached
15
LMBPER 256
CSFRs of CPUs[0 ..15];
CSFRs Mbyte
LMB & Internal Peripheral Space; non-speculative,
INTPER
no execution, non-cached
Data Sheet
39
V1.0, 2008-04