TC1796 Datasheet, PDF (116/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1796
Electrical Parameters
BFCLK Timing and PLL Jitter
The BFCLK timing is important for calculating the timing of an external flash memory. In
principle BFCLK timing can be derived from the PLL jitter formulas. In case of only EBU
synchronous read access to the flash device the worst case jitter is partially lower.
For one BFCLK with a cycle time of 13,33 ns the maximum jitter is
t_JPP = |+/-620 ps|
For two BFCLKs with an accumulated cycle time of 26,66 ns the maximum jitter is
t_JPACC = |+/- 660 ps|
Data Sheet
116
V1.0, 2008-04