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TC1796 Datasheet, PDF (115/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore
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TC1796
Electrical Parameters
4.3.6 BFCLKO Output Clock Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%;
TA = -40 °C to +125 °C; CL = 35 pF
Table 25 BFCLK0 Output Clock Timing Parameters1)
Parameter
Symbol
Min.
Values
Typ. Max.
Unit Note /
Test Con
dition
BFCLKO clock period
tBFCLKO CC 13.332) –
–
ns –
BFCLKO high time
t5
CC 3
–
–
ns –
BFCLKO low time
t6
CC 3
–
–
ns –
BFCLKO rise time
t7
CC –
–
3
ns –
BFCLKO fall time
t8
CC –
BFCLKO duty cycle t5/(t5 + t6)3) DC24 CC 45
–
3
50 55
ns –
% divider of
2, 4, ...4)
BFCLKO duty cycle t5/(t5 + t6)3) DC3 CC 30
33.33 36
% divider of
3 4)
BFCLKO high time reduction5) dt5 CC –
–
1) Not subject to production test, verified by design/characterization.
1.1 ns CL = 20pF
2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to fCPU, the K-divider setting
determines the duty cycle.
4) The division ratio between LMB and BFCLKO frequency is set by EBU_BFCON.EXTCLOCK.
5) Due to asymmetry of the delays and slopes of the rising and falling edge of the pad. The influence of the PLL
jitter is included in this parameter. This parameter should be applied taking the typical value of the duty cycle
in the account, not the minimum or maximum value.
tBFCLKO
BFCLKO 0.5 VDDP05
t5
t6
t8
Figure 34 BFCLKO Output Clock Timing
0.9 VDD
t7
0.1 VDD
MCT04883_mod
Data Sheet
115
V1.0, 2008-04
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