TC1796 Datasheet, PDF (38/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1796
Functional Description
• JEDEC standard based command sequences for PFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
• Margin check for detection of problematic PFLASH bits
Features of the Data Flash
• 128 Kbyte on-chip data Flash memory, organized in two 64 Kbyte banks
• Usable for data storage with EEPROM functionality
• 128 Byte program interface
– 128 bytes are programmed into one DFLASH page by one step/command
• 64-bit read interface (no burst transfers)
• Dynamic correction of single-bit errors during read access
• Detection of double bit errors
• Fixed sector architecture
– Two 64 Kbyte banks/sectors
– Each sector separately erasable
• Configurable read protection (combined with write protection) for complete DFLASH
together with PFLASH read protection
• Password mechanism to temporarily disable write and read protection
• Erasing/programming of one bank possible while reading data from the other bank
• Programming of one bank possible while erasing the other bank
• On-chip generation of programming voltage
• DFLASH is delivered in erased state (read all zeros)
• JEDEC-standard based command sequences for DFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
• Margin check for detection of problematic DFLASH bits
Data Sheet
38
V1.0, 2008-04