TC1796 Datasheet, PDF (50/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1796
Functional Description
3.10
High-Speed Synchronous Serial Interfaces (SSC0, SSC1)
Figure 9 shows a global view of the functional blocks and interfaces of the two High-
Speed Synchronous Serial interfaces SSC0 and SSC1.
Clock
Control
f_SSC0
f_CLC0
Address
Decoder
EIR
Interrupt TIR
Control _RIR
SSC0_RDR
To
DMA ^SSC0_TDR
Clock
Control
f_SSC1
f_CLC1
Address
Decoder
EIR
Interrupt TIR
Control _RIR
SSC1_RDR
To
DMA ^SSC1_TDR
SSC0
Module
(Kernel)
8-Stage RXFIFO
8-Stage TXFIFO
Master
MRSTA
MRSTB
MTSR
Slave
MTSRA
MTSRB
MRST
Slave
Master
Slave
SCLKA
SCLKB
SCLK
SLSI1
SLSI[7:2] ¹⁾
M/S Selected
SSC Enabled
Master
SLSO[7:2]
Master ^SLSO[7:2]
SLSO0
SLSO1
Port 2
Control
SSC1
Module
(Kernel)
Master
MRSTA
MRSTB
MTSR
Slave
MTSRA
MTSRB
MRST
Slave
Master
Slave
SCLKA
SCLKB
SCLK
SLSI1
SLSI[7:2] ¹⁾
Port 6
Control
A2 MRST0
A2 MTSR0
A2 SCLK0
A2 SLSI0
A2 SLSO0
A2 SLSO1
A2
P2.2 /
SLSO2
A2
P2.7 /
SLSO7
A2
P6.4 /
MTSR1
A2
P6.5 /
MRST1
A2
P6.6 /
SCLK1
A2
P6.7 /
SLSI1
1) These lines are not connected
MCA05791
Figure 9 Block Diagram of the SSC Interfaces
The SSC allows full-duplex and half-duplex serial synchronous communication up to
37.5 Mbit/s (@ 75 MHz module clock) with Receive and Transmit FIFO support. (FIFO
only in SSC0). The serial clock signal can be generated by the SSC itself (Master Mode)
Data Sheet
50
V1.0, 2008-04