TC1796 Datasheet, PDF (129/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1796
Electrical Parameters
4.3.12.3 Synchronous Serial Channel (SSC) Master Mode Timing
Table 34
Parameter
SSC Master Mode Timing (Operating Conditions apply), C_L = 50 pF
Symbol
Values
Unit Note /
Min.
Typ. Max.
Test Con
dition
SCLK clock period¹⁾²⁾
t₅₀ CC 2 × T_SSC3) –
–
MTSR/SLSOx delay from
SCLK rising edge
t₅₁ CC 0
–
8
ns –
ns –
MRST setup to SCLK
falling edge
t₅₂ SR 10
–
–
ns –
MRST hold from SCLK
falling edge
t₅₃ SR 5
–
–
ns –
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) SCLK signal high and low times can be minimum 1 × T_SSC.
3) T_SSCmin = T_SYS = 1/f_SYS. When f_SYS = 75 MHz, t₅₀ = 26,67ns
t₅₀
SCLK¹⁾²⁾
t₅₁
t₅₁
MTSR¹⁾
MRST¹⁾
SLSOx²⁾
t₅₂
t₅₃
Data
valid
t₅₁
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_Tmg_1.vsd
Figure 44 SSC Master Mode Timing
Data Sheet
129
V1.0, 2008-04