TC1796 Datasheet, PDF (51/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1796
Functional Description
or can be received from an external master (Slave Mode). Data width, shift direction,
clock polarity and phase are programmable. This allows communication with SPI-
compatible devices. Transmission and reception of data is double-buffered. A shift clock
generator provides the SSC with a separate serial clock signal. One slave select input is
available for Slave Mode operation. Eight programmable slave select outputs (chip
selects) are supported in Master Mode. The I/O lines of the SSC0 module are connected
to dedicated device pins while the SSC1 module I/O lines are wired with general purpose
I/O port lines.
Features
• Master and Slave Mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: Idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Baud rate generation from 37.5 Mbit/s to 572.2 Bit/s (@ 75 MHz module clock)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
• Flexible SSC pin configuration
• One slave select input SLSI in slave mode
• Eight programmable slave select outputs SLSO in Master Mode
– Automatic SLSO generation with programmable timing
– Programmable active level and enable control
• SSC0 with 8-stage receive FIFO (RXFIFO) and 8-stage transmit FIFO (TXFIFO)
– Independent control of RXFIFO and TXFIFO
– 2- to 16-bit FIFO data width
– Programmable receive/transmit interrupt trigger level
– Receive and Transmit FIFO filling level indication
– Overrun error generation
– Underflow error generation
Data Sheet
51
V1.0, 2008-04