TC1796 Datasheet, PDF (112/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1796
4.3.5 Phase Locked Loop (PLL)
Electrical Parameters
Note: All PLL characteristics defined on this and the next page are verified by design
characterization.
Table 24 PLL Parameters (Operating Conditions apply)
Parameter
Symbol
Min.
Values
Typ. Max.
Unit Note /
Test Con
dition
Accumulated jitter
D_P
See
–
–
––
Figure 3
2
VCO frequency range
f_VCO
400
–
500
MHz –
600
–
700
MHz –
PLL base frequency¹⁾
500
f_PLLBASE 140
150
–
600
MHz –
–
320
MHz –
–
400
MHz –
200
–
480
MHz –
PLL lock-in time
t_L
–
–
200
µs –
1) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is
the K factor after reset).
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock f_VCO (and with it the CPU
clock f_CPU) is constantly adjusted to the selected frequency. The relation between f_VCO
and f_SYS is defined by: f_VCO = K × f_CPU. The PLL causes a jitter of f_CPU and affects the
clock outputs BFCLKO, TRCLK, and SYSCLK (P1.12) which are derived from the PLL
clock f_VCO.
There will be defined two formulas that define the (absolute) approximate maximum
value of jitter D_P in ns dependent on the K-factor, the CPU clock frequency f_CPU in MHz,
and the number P of consecutive f_CPU clock periods.
P × K < 385
Dp[ns] = _f---c---p---u--7-₂--0-_[--0M---0---H--^×---z--P-_]---_×-----K--- + 0, 535
(1)
P × K ≥ 385
Dp[ns] = -_f--c---p---u---₂-2--_[-7-M--0---0-H--0---z0---0_]---_×-----K-----₂- + 0, 535
(2)
Data Sheet
112
V1.0, 2008-04