XC2700 Datasheet, PDF(59/62 Page) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

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XC2700 Datasheet, PDF (59/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

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XC2700 Derivatives

XC2000 Family / Alpha Line

Detailed Errata Description

RESET_X.D001 Reset Types of Trap Registers

The reset type of SCU registers TRAPDIS, TRAPSET and TRAPNP is an Application

Reset.

In the next revision of the userâs manual the reset type of this registers will be changed

from a Power-on Reset to an Application Reset.

SCU_X.D007 SCU Interrupts Enabled After Reset

Additional information to the âSCU Interrupt Generationâ chapter of the User's Manual:

Following a reset, the SCU interrupts are enabled by default (register SCU_INTDIS =

0000H). This may lead to interrupt requests being triggered in the SCU immediately,

even before user software has begun to execute. In the SCU, multiple interrupt sources

are `ORed` to a common interrupt node of the CPU interrupt controller. Due to the

âORingâ of multiple interrupt sources, only one interrupt request to the interrupt controller

will be generated if multiple sources at the input of this OR gate are active at the same

time. If user software enables an interrupt in the interrupt controller (SCU_xIC) which

shares the same node as the SCU interrupt request active after reset, it may lead to the

effect of suppressing the intended interrupt source. So, for all SCU interrupt sources

which will not be used, make sure to disable the interrupt source (SCU_INTDIS) and

clear any pending request flags (SCU_xIC.IR) before enabling interrupts in interrupt

controller.

StartUp_X.D002 External Start-Up Mode Selection by Configuration Pins

In âStart-Up Mode Selectionâ section of chapter 10.1 of the user manual version 2.0 the

following table should updated (changes are marked red).

Table 10 Start-Up Mode Configuration

Start-Up Mode

STSTAT.HWCFG Value1) Configuration Pins P10.[4:0]2)

External Start

0000â0000B

1) Bitfield HWCFG can be loaded from Port 10 or from bitfield SWCFG in register SWRSTCON.

2) x means that the level on the corresponding pin is irrelevant.

Errata Sheet

V1.7, 2014-10

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