XC2700 Datasheet, PDF (19/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2700 Derivatives
XC2000 Family / Alpha Line
Detailed Errata Description
BSL_CAN_X.001 Quartz Crystal Settling Time after PORST too Long for
CAN Bootstrap Loader
The startup configuration of the CAN bootstrap loader when called immediately after
PORST limits the settling time of the external oscillation to 0.5 ms. For typical quartz
crystal this settling time is too short. The CAN bootstrap loader generates a time-out and
goes into Startup Error State.
Workaround
• For low performance CAN applications a ceramic resonator with settling time less
than 0.5 ms can be used.
• An alternative is the Internal Start from on-chip Flash memory as startup mode after
PORST. Then switch the system clock to external source and trigger a software reset
with CAN bootstrap loader mode selected. Now the device starts with a CAN
bootstrap loader without limitation of the oscillator settling time.
BSL_X.004 Evaluation of UART Bootstrap Loader Identification Byte in
Single Wire Configuration
In the current implementation, transmission of the start bit of the identification byte (D5_H)
partially overlaps with the stop bit time slot of the zero byte sent by the host. This does
not present any problem in a duplex (2-wire) configuration.
If the UART bootstrap loader is used in a single wire configuration (RxD/TxD externally
connected, e.g. K-line environment), depending on the baudrate, the start bit of the
identification byte may not be correctly recognized by the host. At 9600 Baud, the host
typically interprets the identification byte as F5_H.
Workaround
The host software either should not evaluate the received identification byte, or should
also tolerate values other than D5_H.
DPRAM_X.001 Parity Error Flag for DPRAM
The parity error flag for the dual port memory (DPRAM) does not work correctly. Under
certain conditions bit PECON.PEFDP is set, although there is no error in the DPRAM.
Errata Sheet
19
V1.7, 2014-10