XC2700 Datasheet, PDF (36/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2700 Derivatives
XC2000 Family / Alpha Line
Detailed Errata Description
Workaround
• To avoid a single trial of a remote answer in this case, set MOFCR.FRREN = 1_B and
MOFGPR.CUR = this object.
MultiCAN_TC.035 Different bit timing modes
Bit timing modes (NFCRx.CFMOD=10_B) do not conform to the specification.
When the modes 001_B-100_B are set in register NFCRx.CFSEL, the actual configured
mode and behaviour is different than expected.
Table 6
Bit timing mode
(NFCR.CFSEL)
according to spec
001_B
010_B
011_B
100_B
Value to be written to
NFCR.CFSEL instead
Mode is missing (not
implemented) in
MultiCAN
011_B
100_B
001_B
Measurement
Whenever a recessive edge (transition
from 0 to 1) is monitored on the receive
input the time (measured in clock
cycles) between this edge and the
most recent dominant edge is stored in
CFC.
Whenever a dominant edge is received
as a result of a transmitted dominant
edge the time (clock cycles) between
both edges is stored in CFC.
Whenever a recessive edge is
received as a result of a transmitted
recessive edge the time (clock cycles)
between both edges is stored in CFC.
Whenever a dominant edge that
qualifies for synchronization is
monitored on the receive input the time
(measured in clock cycles) between
this edge and the most recent sample
point is stored in CFC.
Workaround
None.
Errata Sheet
36
V1.7, 2014-10