XC2700 Datasheet, PDF (41/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2700 Derivatives
XC2000 Family / Alpha Line
Detailed Errata Description
RTCIR will get set if at least one of the individual interrupt requests (flags CNTxIR,
T14IR) was pending.
USIC_AI.003 TCSRL.SOF and TCSRL.EOF not cleared after a transmission
is started
The Start of Frame (SOF) and End of Frame (EOF) bit in the Transmit Control/Status
Register (TCSRL) will not be cleared by hardware when the data is transfered from the
transmit buffers (TBUFx) to the transmit shift register, i.e. the transmission of a new word
starts.
Workaround
Clear TCSRL.SOF and TCSRL.EOF by software.
USIC_AI.004 Receive shifter baudrate limitation
If the frame length of SCTRH.FLE does not match the frame length of the master, then
the baudrate of the SSC slave receiver is limited to f_sys/2 instead of f_sys.
Workaround
None.
USIC_AI.005 Only 7 data bits are generated in IIC mode when TBUF is
loaded in SDA hold time
When the delay time counter is used to delay the data line SDA (HDEL > 0), and the
empty transmit buffer TBUF was loaded between the end of the acknowledge bit and the
expiration of programmed delay time HDEL, only 7 data bits are transmitted.
With setting HDEL=0 the delay time will be t_HDEL = 4 x 1/f_SYS + delay (approximately 60ns
@ 80MHz).
Workaround
• Do not use the delay time counter, i.e use only HDEL=0 (default),
or
• write TBUF before the end of the last transmission (end of the acknowledge bit) is
reached.
Errata Sheet
41
V1.7, 2014-10