XC2700 Datasheet, PDF (27/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2700 Derivatives
XC2000 Family / Alpha Line
Detailed Errata Description
Task A
Global Bank
Task B
Local Bank
Task C
Global Bank
Task A
Global Bank
Task B
SCXT ^Interrupt
CP
Register Bank
Validation,
interrupted...
Task C
Interrupt
RETI
Task B
Register Bank
Validation,
… finished
RETI
Task C
Task C Delayed!
Figure 2 Example for Case 2: Interrupt Service for Task C delayed
Workaround for Case 1
Do not write to the CP register (i.e. modify the context of a global bank) while a local
register bank context is selected.
Workaround for Case 2
When using both local and global register banks via the bank selection registers
BNKSEL0...3 for interrupts on levels ≥12, ensure that there is no interrupt using a global
register bank that has a higher priority than an interrupt using a local register bank.
Example 1:
Local bank interrupts are used on levels 14 and 15, no local bank interrupts on level 12
and 13. In this case, global bank interrupts on level 15 must not be used.
Example 2:
Local bank interrupts are used on level 12. In this case, no global bank interrupts must
be used on levels 13, 14, 15.
INT_X.010 HW Traps and Interrupts may get postponed
Under the special conditions described below, a hardware trap (HWTx) and subsequent
interrupts, PEC transfers, OCDS service requests (on priority level < 11_H) or class B and
class A traps (if HWTx also was class A) may get postponed until the next RETI
instruction is executed. If no RETI is executed, these requests may get postponed
infinitely.
Errata Sheet
27
V1.7, 2014-10