XC2700 Datasheet, PDF (20/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2700 Derivatives
XC2000 Family / Alpha Line
Detailed Errata Description
Workaround
Do not enable the parity error trap for the dual port memory, i.e. leave bit
PECON.PEENDP = 0 (default after power-on reset).
EBC_X.007 Bus Arbitration not Properly Working
Due to a mismatch of pad propagation delays and internal operation cycle time the
arbitration feature of the External Bus Controller (EBC) can only be used with severe
restrictions. It is recommended not to use this feature, as future members of the
XC2000/XE166 Family will no longer support bus arbitration.
Workaround
The usable conditions also depend on the application system and can only be defined
for a specific use case.
ESR_X.004 Wrong Value of SCU_RSTCONx Registers after ESRy Applica-
tion Reset
SCU_RSTCONx registers are reset only by Power-On, but they may be wrongly affected
after a second application reset requested by an ESRy pin. This may lead to the
SCU_RSTCONx register values being set to zero, which could unexpectedly disable reset
sources within the user application. The conditions which lead to this behavior are:
1. First, an application reset by SW (software), CPU (Central Processing Unit), MP
(Memory), WDT (Watchdog Timer) or ESRy (External Service Request y) occurs.
2. Following this, an application reset on an ESRy pin occurs.
3. If the above mentioned ESRy reset occurs during a critical time window of the SSW
(startup software), then it’s possible that the application will operate with the wrong
SCU_RSTCONx register value. The critical time window occurs when the SSW is
writing the SCU_RSTCONx registers, and at the same time, the ESRy reset request is
processed by the reset circuitry. The width of this critical window f_{critical window} is less
than 13 cycles.
Errata Sheet
20
V1.7, 2014-10