XC2700 Datasheet, PDF (24/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2700 Derivatives
XC2000 Family / Alpha Line
Detailed Errata Description
Example
A request from the OCDS to enter Suspend Mode (request source OCDS entry, priority
14) will be ignored if (at any time before) an interrupt request has occurred (request
source ITC, priority 9), and the ITC request trigger is enabled in register GSCEN. In this
case, modules that are programmed to stop in Suspend Mode (selected in bit field
SUMCFG) will continue to run.
Workaround
Disable triggers from request sources that are not used by the application in register
GSCEN.
For other sources that shall trigger the GSC, clear and then set again the respective
trigger enable bits in register GSCEN each time the GSC logic shall be armed.
INT_X.007 Interrupt using a Local Register Bank during execution of IDLE
During the execution of the IDLE instruction, if an interrupt which uses a local register
bank is acknowledged, the CPU may stall, preventing further code execution. Recovery
from this condition can only be made through a hardware or watchdog reset.
All of the following conditions must be present for the problem to occur:
• The IDLE instruction is executed while the global register bank is selected (bit field
BANK = 00_B in register PSW),
• The interrupting routine is using one of the local register banks (BANK = 10_B or 11_B),
and the local register bank is selected automatically via the bank selection registers
BNKSEL0...3, (i.e. the interrupting routine has a priority level ≥12),
• The system stack is located in the internal dual-ported RAM (DPRAM, locations
0F600_H ... 0FDFF_H),
• The interrupt is acknowledged during the first 8 clock cycles of the IDLE instruction
execution.
Workaround 1
Disable interrupts (either globally, or only interrupts using a local register bank) before
execution of IDLE:
BCLR IEN
IDLE
BSET IEN
; Disable interrupts globally
; CPU enters idle mode
; After exit from idle mode
; re-enable interrupts
If an interrupt request is generated during this sequence, the CPU leaves idle mode and
acknowledges the interrupt after BSET IEN.
Errata Sheet
24
V1.7, 2014-10