XC2700 Datasheet, PDF (39/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2700 Derivatives
XC2000 Family / Alpha Line
Detailed Errata Description
For Flash and CPU, bitfield SUMCFG must be configured to normal mode anyway, since
they are required for debugging.
Workaround
None.
RESET_X.002 Startup Mode Selection is not Valid in SCU_STSTAT.HWCFG
Reading from SCU_STSTAT.HWCFG-bitfield returns all zeros instead of the information
which startup mode has been entered after the last reset.
Workaround
Read the initial value from VECSEG register to evaluate where from the user code is
started:
• VECSEG[7:0]=00_H - start from an off-chip memory, external startup mode
• VECSEG[7:0]=C0_H - start from on-chip flash, internal startup mode
• VECSEG[7:0]=E0_H - start from on-chip PSRAM, bootstrap loader mode
(UART, CAN or SSC)
RESET_X.003 P2.[2:0] and P10.[12:0] Switch to Input
During the execution of an Application Reset and Debug Reset the pins P2.[2:0] and
P10.[12:0] are intermediately switched to input.
These pins return to their previous mode approximately 35 system clock cycles after the
application reset counter has expired (approx. 0.6 µs with default reset delay at 80 MHz).
If such a pin is used as output, make sure that this short interruption does not lead to
critical system conditions.
Workaround
External pull devices can be added to have a defined level on these pins during
Application and Debug Reset.
Errata Sheet
39
V1.7, 2014-10