XC2700 Datasheet, PDF (48/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2700 Derivatives
XC2000 Family / Alpha Line
Detailed Errata Description
After execution of this algorithm, Timer_high and Timer_low represent a consistent time
stamp of the concatenated timers.
The equivalent number of system clock cycles corresponding to two basic clock cycles
is shown in the following Table 7:
Table 7
Equivalent Number of System Clock Cycles Required to Wait for Two
Basic Clock Cycles
Setting of BPS1
BPS1 = 01 BPS1 = 00 BPS1 = 11 BPS1 = 10
Required Number of System 8
Clocks
16
32
64
Setting of BPS2
BPS2 = 01 BPS2 = 00 BPS2 = 11 BPS2 = 10
Required Number of System 4
8
16
32
Clocks
In case the required timer resolution can be achieved with different combinations of the
Block Prescaler BPS1/BPS2 and the Individual Prescalers TxI, the variant with the
smallest value for the Block Prescaler may be chosen to minimize the waiting time. E.g.
in order to run T6 at f_SYS/512, select BPS2 = 00_B, T6I = 111_B, and insert 8 NOPs (or other
instructions) to ensure the required waiting time before reading Timer_high the second
time.
INT_X.H002 Increased Latency for Hardware Traps
When a condition for a HW trap occurs (i.e. one of the bits in register TFR is set to 1_B),
the next valid instruction that reaches the Memory stage is replaced with the
corresponding TRAP instruction. In some special situations described in the following, a
valid instruction may not immediately be available at the Memory stage, resulting in an
increased delay in the reaction to the trap request:
1. When the CPU is in break mode, e.g. single-stepping over such instructions as SBRK
or BSET TFR.x (where x = one of the trap flags in register TFR) will have no
(immediate) effect until the next instruction enters the Memory stage of the pipeline
(i.e. until a further single-step is performed).
2. When the pipeline is running empty due to (mispredicted) branches and a relatively
slow program memory (with many wait states), servicing of the trap is delayed by the
time for the next access to this program memory, even if vector table and trap handler
are located in a faster memory. However, the situation when the pipeline/prefetcher
are completely empty is quite rare due to the advanced prefetch mechanism of the
C166S V2 core.
Errata Sheet
48
V1.7, 2014-10