XC2700 Datasheet, PDF (54/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2700 Derivatives
XC2000 Family / Alpha Line
Detailed Errata Description
RAM and most of the MultiCAN registers are no longer supported. A normal continuation
when the suspend mode is left may not always be possible and may require a reset (e.g.
depending on error counters).
PVC_X.H001 PVC Threshold Level 2
The Power Validation Circuits (PVCM, PVC1) compare the supply voltage of the
respective domain (DMP_M, DMP_1) with programmable levels (LEV1V and LEV2V in
register SCU_PVCMCON0 or SCU_PVC1CON0).
The default value of LEV1V is used to generate a reset request in the case of low core
voltage.
LEV2V can generate an interrupt request at a higher voltage, to be used as a warning.
Due to variations of the tolerance of both the Embedded Voltage Regulators (EVR) and
the PVC levels, this interrupt can be triggered inadvertently, even though the core
voltage is within the normal range. It is, therefore, recommended not to use this warning
level.
LEV2V can be disabled by executing the following sequence:
1. Disable the PVC level threshold 2 interrupt request SCU_PVCMCON0.L2INTEN and
SCU_ PVC1CON0.L2INTEN.
2. Disable the PVC interrupt request flag source SCU_INTDIS.PVCMI2 and
SCU_INTDIS.PVC1I2.
3. Clear the PVC interrupt request flag source SCU_DMPMITCLR.PVCMI2 and SCU_
DMPMITCLR.PVC1I2.
4. Clear the PVC interrupt request flag by writing to SCU_INTCLR.PVCMI2 and
SCU_INTCLR.PVC1I2.
5. Clear the selected SCU request flag (default is SCU_1IC.IR).
The Power Validation Circuits (PVCM) compare the supply voltage of the respective
domain (DMP_M) with programmable levels (LEV1V and LEV2V in register
SCU_PVCMCON0).
The default value of LEV1V is used to generate a reset request in the case of low core
voltage.
LEV2V can generate an interrupt request at a higher voltage, to be used as a warning.
Due to variations of the tolerance of both the Embedded Voltage Regulators (EVR) and
the PVC levels, this interrupt can be triggered inadvertently, even though the core
voltage is within the normal range. It is, therefore, recommended not to use this warning
level.
LEV2V can be disabled by executing the following sequence:
1. Disable the PVC level threshold 2 interrupt request SCU_PVCMCON0.L2INTEN.
2. Disable the PVC interrupt request flag source SCU_INTDIS.PVCMI2.
Errata Sheet
54
V1.7, 2014-10