XC2700 Datasheet, PDF (51/62 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller

XC2700 Derivatives
XC2000 Family / Alpha Line
Detailed Errata Description
MultiCAN_AI.H006 Time stamp influenced by resynchronization
The time stamp measurement feature is not based on an absolute time measurement,
but on actual CAN bit times which are subject to the CAN resynchronization during CAN
bus operation.The time stamp value merely indicates the number of elapsed actual bit
times. Those actual bit times can be shorter or longer than nominal bit time length due
to the CAN resynchronization events.
Workaround
None.
MultiCAN_AI.H007 Alert Interrupt Behavior in case of Bus-Off
The MultiCAN module shows the following behavior in case of a bus-off status:
TEC=0x60 or
REC=0x60
EWRN
REC=0x1,
TEC=0x1
BOFF
INIT
REC=0x60,
TEC=0x1
EWRN+BOFF
INIT
REC=0x0,
TEC=0x0
ALERT
INIT
Figure 5 Alert Interrupt Behavior in case of Bus-Off
When the threshold for error warning (EWRN) is reached (default value of Error Warning
Level EWRN = 0x60), then the EWRN interrupt is issued. The bus-off (BOFF) status is
reached if TEC > 255 according to CAN specification, changing the MultiCAN module
with REC and TEC to the same value 0x1, setting the INIT bit to 1_B, and issuing the
BOFF interrupt. The bus-off recovery phase starts automatically. Every time an idle time
is seen, REC is incremented. If REC = 0x60, a combined status EWRN+BOFF is
reached. The corresponding interrupt can also be seen as a pre-warning interrupt, that
the bus-off recovery phase will be finished soon. When the bus-off recovery phase has
finished (128 times idle time have been seen on the bus), EWRN and BOFF are cleared,
the ALERT interrupt bit is set and the INIT bit is still set.
MultiCAN_AI.H008 Effect of CANDIS on SUSACK
When a CAN node is disabled by setting bit NCR.CANDIS = 1_B, the node waits for the
bus idle state and then sets bit NSR.SUSACK = 1_B.
Errata Sheet
51
V1.7, 2014-10