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ICSSSTUB32866B Datasheet, PDF (9/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2 | |||
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ICSSSTUB32866B
Advance Information
2. Device standard (cont'd)
G2
RST
H1
CK
J1
CK
D1â¢D6,
D8-D13
V REF
11
A3, T3
G5
C1
G1
P AR_IN
LPS0
(internal node)
D CE
CK Q
R
11
D1â¢D6,
D8â¢D13
Parity
Generator
D1â¢D6,
D8â¢D13
11
0
DQ
1
CK
R
DQ
CK
R
CE
1
D Q0
CK
R
11 Q1Aâ¢Q6A,
Q8Aâ¢Q13A
11 Q1Bâ¢Q6B,
Q8Bâ¢Q13B
A2
PPO
D2
QERR
G6
C0
CK
2â¢Bit
Counter
R
LPS1
(internal node)
0
D
Q
1
CK
R
Figure 8 Parity logic diagram for 1:2 register-B configuration (positive logic); CO=1, C1=1
1165â10/25/06
9
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