ICSSSTUB32866B Datasheet, PDF (13/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
2. Device standard (cont'd)
RST
DCS
CSR
n
n+1
n+2
n+3
n+4
CK
CK
D1•D14 ^†
Q1•Q14
PAR_IN ^†
PPO
QERR# ^‡
(not used)
tact
tsu
th
tpdm , t _pdmss
CK to Q
tsu
tPHL
CK to QERR
Data to QERR#
Latency
H, L, or X
th
tpd
CK to PPO
tPHL , t _PLH
CK to QERR
H or L
Figure 12 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in
pair; C0=0, C1=1; RST switches from L to H
†
‡
1165—10/25/06
After RST is switched from low to high, all data and PAIR_IN inputs signals must be set and held low for a minimum time of t_ACT
max, to avoid false error
If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on
the n+2 clock pulse.
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