ICSSSTUB32866B Datasheet, PDF (5/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

Block Diagram for 1:1 mode (positive logic)
RST
CK
CK
VREF
DCKE
DODT
DCS
CSR
ICSSSTUB32866B
Advance Information
D
C1
R
D
C1
R
1D
C1
R
QCKEA
QOTDA
QCSA#
D1
O
1
1D
C1
R
Q1A
(1)
Q1B
1165—10/25/06
TO 21 OTHER CHANNELS
NOTE:
1. Disabled in 1:1 configuration.
5