ICSSSTUB32866B Datasheet, PDF (10/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
2. Device standard (cont'd)
RST
DCS
CSR
CK
CK
tact
D1•D25 ^†
Q1•Q25
PAR_IN ^†
PPO
QERR ^‡
n
n+1
n+2
n+3
n+4
tsu
th
tpdm , t _pdmss
CK to Q
tsu
th
tpd
CK to PPO
tPHL
CK to QERR
Data to QERR Latency
tPHL , t _PLH
CK to QERR
H, L, or X
H or L
Figure 9 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
RST Switches from L to H
† ^{After RST is switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t} _ACT
max, to avoid false error.
‡ If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
1165—10/25/06
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