ICSSSTUB32866B Datasheet, PDF (26/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
DUT
Out
CL = 5pF ⁽¹⁾
Test Point
RL = 1KΩ
Partial parity out load circuit
CLK
CLK
Output
VICR
tHL
VTT
VICR
tHL
VI(PP)
VTT
VTT = VDD/2
VI(P-P) = 600mV
tPLH and tPHL are the same as tPD
Partial parity out voltage waveform, propagation
delay time with respect to CLK input
LVCMOS RESET
Input
VIH
VDD/2
Output
tPHL
VTT
VIL
VOH
VOL
VTT = VDD/2
tPLH and tPHL are the same as tPD
VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs.
1165—10/25/06
Partial parity out voltage waveform, propagation
delay time with respect to RESET input
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