ICSSSTUB32866B Datasheet, PDF (16/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
2. Device standard (cont'd)
RST#
DCS#
CSR#
CK
n
n+1
n+2
n+3
n+4
CK#
D1•D14 ^†
Q1•Q14
PAR_IN ^†‡
PPO
(not used)
QERR# ^§
tact
tsu
th
tpdm , t _pdmss
CK to Q
tsu
th
tpd
CK to PPO
tPHL
CK to QERR#
Data to QERR# Latency
tPHL , t _PLH
CK to QERR#
H, L, or X
H or L
Figure 15 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in
pair; C0=1, C1=1; RST# switches from L to H
†
After RST# switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t
max, to avoid false error.
ACT
‡
PAR_IN is driven from PPO of the first SSTU32866 device.
§
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
1165—10/25/06
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