ICSSSTUB32866B Datasheet, PDF (18/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
2. Device standard (cont'd)
RST#
DCS# ^†
tinact
CSR# ^†
CK ^†
CK# ^†
D1•D14 ^†
Q1•Q14
tRPHL
RST# to Q
PAR_IN ^†
PPO
(not used)
tRPHL
RST# to PPO
QERR#
tRPLH
RST# to QERR#
H, L, or X
H or L
Figure 17 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in
pair; C0=1, C1=1; RST# switches from H to L
†
After RST# is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a
munimum time of t _INACT max.
1165—10/25/06
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