ICSSSTUB32866B Datasheet, PDF (8/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
2. Device standard (cont'd)
G2
RST
CK ^H1
CK ^J1
D2•D3,
D5•D6,
D8-D14
V _REF
11
A3, T3
G5
C1
G1
P AR_IN
LPS0
(internal node)
D ^CE
CK Q
R
11
D2•D3,
D5•D6,
D8•D14
Parity
Generator
D2•D3,
D5•D6,
D8•D14
11
0
DQ
1
CK
R
DQ
CK
R
CE
1
DQ 0
CK
R
Q2A•Q3A,
11 _{Q5A•Q6A,}
Q8A•Q14A
11 _{Q2B•Q3B,}
Q5B•Q6B,
Q8B•Q14B
A2
PPO
D2
QERR
G6
C0
CK
2•Bit
Counter
R
LPS1
(internal node)
0
D
Q
1
CK
R
Figure 7 — Parity logic diagram for 1:2 register-A configuration (positive logic); C0=0, C1=1
1165—10/25/06
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