ICSSSTUB32866B Datasheet, PDF (1/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

Integrated
Circuit
Systems, Inc.
ICSSSTUB32866B
Advance Information
25-Bit Configurable Registered Buffer for DDR2
Recommended Application:
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS97ULP877
• Ideal for DDR2 400,533,667 and 800
Product Features:
• 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity check functionality
• Supports SSTL_18 JEDEC specification on data
inputs and outputs
• Supports LVCMOS switching levels on CSR and
RESET inputs
• Low voltage operation
V_DD = 1.7V to 1.9V
• Available in 96 BGA package
• Drop-in replacement for ICSSSTUA32864
• Green packages available
Functionality Truth Table
Inputs
Dn,
RST DCS CSR
CK
CK DODT, Qn
DCKE
H
L
L
↑
↓
L
L
H
L
L
↑
↓
H
H
H
L
L
L or H L or H
X
Q0
H
L
H
↑
↓
L
L
H
L
H
↑
↓
H
H
H
L
H
L or H L or H
X
Q0
H
H
L
↑
↓
L
L
H
H
L
↑
↓
H
H
H
H
L
L or H L or H
X
Q0
H
H
H
↑
↓
L
Q0
H
H
H
↑
↓
H
Q0
H
H
H
L or H L or H
X
Q0
L
X or X or
X or X or
X or
L
Floating Floating Floating Floating Floating
Outputs,
QCS
L
L
Q0
L
L
Q0
H
H
Q0
H
H
Q0
L
QODT,
QCKE
L
H
Q0
L
H
Q0
L
H
Q0
L
H
Q0
L
Pin Configuration
123456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
96 Ball BGA
(Top View)
1165—10/25/06
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
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