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ICSSSTUB32866B Datasheet, PDF (22/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2 | |||
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ICSSSTUB32866B
Advance Information
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
fclock
tW
tACT
tINACT
tsu
tsu
tsu
tsu
tsu
tH
Notes:
Clock frequency
Pulse duration, CK, CK HIGH or LOW
Differential inputs active time (See Notes 1 and 2)
Differential inputs inactive time (See Notes 1 and 3)
Setup time
Setup time
Setup time
Setup time
Setup time
DSR# before CKâ, CK#â,
CSR# high
CSR# before CKâ, CK#â,
DCS# high
DCS# before CKâ, CK#â,
CSR# low
DODT, DCKE and data before
CKâ, CK#â
PAR_IN before CKâ, CK#â
Hold time
DCS#, DODT, DCKE and Q
after CKâ, CK#â
Hold time
PAR_IN after CKâ, CK#â
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
VDD = 1.8V ±0.1V
MIN MAX
-
410
1
-
-
10
-
15
0.6
0.6
0.5
0.5
0.5
0.40
0.40
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN MAX
fmax Max input clock frequency
410
tPDM
Propagation delay, single CKâ to CK#â QN
bit switching
1.1
1.9
tPD Propagation delay
CKâ to CK#â to PPO
0.5
1.8
tLH
Low to High propagation CKâ to CK#â to QERR#
delay
1.2
3
tHL
High to low propagation
delay
CKâ to CK#â to QERR#
1
2.4
tPDMSS
Propagation delay
simultaneous switching
CKâ to CK#â QN
-
2
tPHL
High to low propagation
delay
Rst# â to QNâ
3
tPHL
High to low propagation
delay
Rst# â to PPOâ
3
Low to High propagation
tPLH delay
Rst# â to QERR#â
3
2. Guaranteed by design, not 100% tested in production.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
1165â10/25/06
22
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