ICSSSTUB32866B Datasheet, PDF (25/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
DUT
Out
VDD
RL = 1KΩ
Test Point
CL = 10 pF ⁽¹⁾
Load Circuit, error output measurements
LVCMOS
VCC
RESET#
VCC/2
0V
tPLH
VOH
Output
Waveform 2
0.15V
0V
Voltage Waveforms, open-drain output LOW-to-HIGH with respect to RESET# input
Timing Inputs
VICR
tHL
VICR
VI(PP)
Output
Waveform 1
VCC/2
VCC
VOL
Voltage Waveforms, open-drain output HIGH-to-LOW with respect to clock inputs
Timing Inputs
VICR
VICR
VI(PP)
tHL
VOH
Output
Waveform 2
0.15V
0V
Voltage Waveforms, open-drain output LOW-to-HIGH with respect to clock inputs
Notes: 1. C_L includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, Z_O =
50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
1165—10/25/06
25