ICSSSTUB32866B Datasheet, PDF (24/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
DUT
Out
VDD
RL = 50Ω
Test Point
CL = 10 pF ⁽¹⁾
LOAD CIRCUIT - HIGH-TO-LOW SLEW-RATE MEASUREMENT
Output
VOH
80%
20%
dv_f
VOL
dt_f
VOLTAGE WAVEFORMS
HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out
(1)
CL = 10 pF
Test Point
RL = 50Ω
LOAD CIRCUIT - LOW-TO-HIGH SLEW-RATE MEASUREMENT
dv_r
dt_r
VOH
80%
20%
Output
VOL
VOLTAGE WAVEFORMS
LOW-TO-HIGH SLEW-RATE MEASUREMENT
Figure 7 ⎯ Output Slew-Rate Measurement Information (V_DD = 1.8V ± 0.1V)
Notes: 1. C_L includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, Z_O =
50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
1165—10/25/06
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