ICSSSTUB32866B Datasheet, PDF (11/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
2. Device standard (cont'd)
RST
DCS
CSR
n
n+1
n+2
n+3
n+4
CK
CK
D1•D25
Q1•Q25
PAR_IN
PPO
QERR ^†
tsu
th
tpdm , t _pdmss
CK to
tsu
th
tpd
CK to PPO
Data to PPO Latency
Data to QERR Latency
tPHL or t _PLH
CK to QERR
Unknown input
event
Output signal is dependent on
the prior unknown input event
H or L
Figure 10
Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
RST being held high
†
If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RST is driven low.
1165—10/25/06
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