ICSSSTUB32866B Datasheet, PDF (23/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
CK Inputs
TL = 50Ω
Test Point
RL = 100Ω
Test Point
DUT
CK#
CK
Out
TL = 350ps, 50Ω
(1)
CL = 30 pF
LOAD CIRCUIT
VDD
RL = 1000Ω
Test Point
RL = 1000Ω
LVCMOS
RST#
Input
IDD ⁽²⁾
VDD/2
tINACT
10%
VDD/2
VDD
0V
tACT
90%
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
CK#
CK
Output
VICR
VICR
VID
tPLH
tPHL
VOH
VTT
VTT
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Input
CK#
CK
Input
tW
VICR
VICR
VID
VOLTAGE WAVEFORMS
PULSE DURATION
tSU
VREF
VICR
tH
VID
VIH
VREF
VIL
LVCMOS
VIH
RST#
VDD/2
Input
VIL
tRPHL
Output
VOH
VTT
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Figure 6 ⎯ Parameter Measurement Information (V_DD = 1.8V ± 0.1V)
Notes: 1. C_L incluces probe and jig capacitance.
2. I_DD tested with clock and data inputs held at V_DD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz,
Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. V_REF = V_DD/2
6. V_IH = V_REF + 250 mV (ac voltage levels) for differential inputs. V_IH = V_DD for LVCMOS input.
7. V_IL = V_REF - 250 mV (ac voltage levels) for differential inputs. V_IL = GND for LVCMOS input.
8. V_ID = 600 mV
9. t_PLH and t_PHL are the same as t_PDM.
1165—10/25/06
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