ICSSSTUB32866B Datasheet, PDF (12/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
2. Device standard (cont'd)
RST
DCS ^†
CSR ^†
tinact
CK ^†
CK ^†
D1•D25 ^†
Q1•Q25
PAR_IN ^†
PPO
tRPHL
RST to Q
tRPHL
RST to PPO
QERR
tRPLH
RST to QERR
H, L, or X
H or L
Figure 11 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
RST switches from H to L
†
After RST is switched from high to low, all data and clock unouts signals must be set and held at valid logic levels (not floating) for
a minimum time of tINACT max.
1165—10/25/06
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