ICSSSTUB32866B Datasheet, PDF (4/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
Ball Assignment
Terminal Name
GND
V_DD
V_REF
Z_OH
Z_OL
CK
CK
C0, C1
RST
CSR, DCS
D1 - D25
DODT
DCKE
Q1 - Q25
QCS
QODT
QCKE
PPO
PAR_IN
QERR
Description
Electrical
Characteristics
Ground
Ground input
Power supply voltage
1.8V nominal
Input reference voltage
0.9V nominal
Reserved for future use
Input
Reserved for future use
Input
Positive master clock input
Differential input
Negative master clock input
Differential input
Configuration control inputs
LVCMOS inputs
Asynchronous reset input - resets registers and disables V_REF data and
clock differential-input receivers
LVCMOS input
Chip select inputs - disables D1 - D24 outputs switching when both inputs
are high
SSTL_18 input
Data input - clock in on the crossing of the rising edge of CK and the
falling edge of CK
SSTL_18 input
The outputs of this register bit will not be suspended by the DCS and
CSR control
SSTL_18 input
The outputs of this register bit will now be suspended by the DCS and
CSR control
SSTL_18 input
Data ouputs that are suspended by the DCS and CSR control
1.8V CMOS
Data output that will not be suspended by the DCS and CSR control
1.8V CMOS
Data output that will not be suspended by the DCS and CSR control
1.8V CMOS
Data output that will not be suspended by the DCS and CSR control
1.8V CMOS
Partial parity out indicates off parity of inputs D1 - D25.
1.8V CMOS
Parity input arrives one clock cycle after the corresponding data input
SSTL_18 input
Output error bit-generated one clock cycle after the corresponding data Open drain
output
output
1165—10/25/06
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