ICSSSTUB32866B Datasheet, PDF (7/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
2. Device standard (cont'd)
G2
RST
H1
CK
CK ^J1
D2•D3,
D5•D6,
D8-D25
V _REF
22
A3, T3
LPS0
(internal node)
D ^CE
CK Q
R
22
D2•D3,
D5•D6,
D8•D25
G5
C1
G1
P AR_IN
Parity
Generator
0
DQ
1
CK
R
D2•D3,
D5•D6,
D8•D25
22
DQ
CK
R
CE
1
DQ 0
CK
R
Q2 Q3,
22 _{Q5 Q6,}
Q8 Q25
A2
PPO
D2
QERR
G6
C0
CK
2•Bit
Counter
R
LPS1
(internal node)
0
DQ
1
CK
R
Figure 6 Parity logic diagram for 1:1 register configuration (positive logic): C0=0, C1=0
1165—10/25/06
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