ICSSSTUB32866B Datasheet, PDF (15/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
2. Device standard (cont'd)
RST#
DCS# ^†
tinact
CSR# ^†
CK ^†
CK# ^†
D1•D14 ^†
Q1•Q14
tRPHL
RST# to Q
PAR_IN ^†
PPO
tRPHL
RST# to PPO
QERR#
(not used)
tRPLH
RST# to QERR#
H, L, or X
H or L
Figure 14 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in
pair; C0=0, C1=1; RST# switches from H to L
†
After RST# is switched from high to low, all data and clock inputs signals must be held at valid logic levels (not floating) for a
minimum time of t_INACT max
1165—10/25/06
15