ICSSSTUB32866B Datasheet, PDF (27/28 Pages) Integrated Circuit Systems – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32866B
Advance Information
A1
D
SEATING
PLANE
C
T
b REF
d TYP
D1
Numeric Designations
for Horizontal Grid
4321
A
B
C
D
Alpha Designations
for Vertical Grid
(Letters I, O, Q, and
S not used)
-e- TYP
TOP VIEW
E
h TYP
c REF
-e- TYP
0.12 C
E1
ALL DIMENSIONS IN MILLIMETERS
----- BALL GRID -----
Max.
D
E
T
e
HORIZ
VERT
TOTAL
d
Min/Max
Min/Max
13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc
6
16
96
0.40/0.50
11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc
6
16
96
0.35/0.45
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
h
Min/Max
0.25/0.41
0.25/0.35
REF. DIMENSIONS
b
c
0.75
0.875
0.75
0.875
10-0055C
Ordering Information
* Source Ref.: JEDEC Publication 95, MO-205
ICSSSTUB32866Bz(LF)T
Example:
ICS XXXX y z (LF) T
1165—10/25/06
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
H = LFBGA (standard size: 5.5 x 13.50)
HM = TFBGA (reduced size: 5.0 x 11.50)
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
27