RF60 Datasheet, PDF (89/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
24. On-Chip Registers
There are two register regions on chip:
Special Function Registers region
XREG region
24.1. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the RF60's resources and peripherals. The
CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as implementing
additional SFRs used to configure and access the sub-systems unique to the RF60. This allows the addi-
tion of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 24.2 lists the
SFRs implemented in the RF60 device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, P1, ACC, IE, etc.) are bit-address-
able as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the
SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and
should be avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 24.2, for a
detailed description of each register.
Table 24.1. Special Function Register (SFR) Memory Map
Color coding of the SFR register map table:
IE <-- Bit addressable registers
MSB
LSB
0x80
0
P0
1
SP
2
DPL
3
DP H
4
GFM_DATA
5 GFM_CONST
6 SBOX_DATA
7
PCON
8
9
A
PROT0_CTRL B
C
D
E
F CLKOUT_SET
0x90
P1
RBIT_DATA
FC_CTRL
RTC_CTRL
FC _I NTER VA L
0xA0
P2
0xB0
GPR_CTRL
GPR_DATA
P0CON
P1CON PORT_CTRL
PORT_SET
PORT_INTCFG
IE
IP
ODS_CTRL TMR3CTRL
ODS_TIMING
T MR3 RL
ODS_DATA
TMR3RH
ODS_RATEL
TMR3L
ODS_RATEH
TMR3H
ODS_WARM1
SYSGEN
ODS_WARM2 INT_FLAGS
0xC0
TMR2CTRL
TMR_CLKSEL
T MR2 RL
TMR2RH
TMR2L
TMR2H
PA_LVL
0xD0
PSW
BOOT_FLAGS
0xE0
ACC
LC_FSK
EIE1
SYS_SET
0xF0
B
EIP1
Tel: [phone]
Fax: [phone]
89
E-mail: [e-mail] http://www.hoperf.com