RF60 Datasheet, PDF (72/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
22. Memory Organization
The memory organization of the RF60 is similar to that of a standard 8051. There are two separate mem-
ory spaces: program memory and data memory. Program and data memory share the same address
space but are accessed via different instruction types. However, this device is unique since it has the pro-
gram and data memory spaced combined into one. This is called a unified CODE and XDATA memory.
The device has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Apart from the CPU core related internal memory, the device has the following memories:
4.5KB of RAM..it can be used both as program CODE and external data XDATA memory
12KB of ROM.. it holds the API (Application Programming Interface) routines.
The ROM is not readable by the user.
256B hardware control registers mapped to XDATA address space
8KB of one time programmable (OTP) non-volatile memory (NVM)
128 bits of multiple time programmable (MTP) EEPROM. Each bit can change value at most 50,000
times.
See Figure 22.1 for the MCU system memory map:
MCU view of unified RAM address space
CODE/
XDATA
XDATA
DATA/IDATA
0x0000
0x11FF _{RAM 4.5K}
0x4000
0x0000
0x4000
0x40FF
XREG
0x8000
0xAFFF
ROM 12K
0x8000
0x00
0x1F
0x20
0x2F
0x30
0x7F
0x80
Registers
Bit
Addressable
Direct &
Inidirect
Addressing
SFR
(DATA) Direct
Addressing Only
0xFF
Lower 128 RAM
bytes,
Direct and Indirect
Addressing
0x80
Upper 128
RAM
Indirect
Addressing
Only
0xFF
0xC000
0xFFFF
0xFFFF
NVM (OTP) 8K
MTP (EEPROM)
128 bits
Figure 22.1. Address Space Map after the Boot
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