RF60 Datasheet, PDF (138/157 Pages) –

TMR_CLKSEL
RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
clk_sys
clk_sys/12
rtc_tick (5.33us)
rtc_pulse (100us)
2
0
1
2
3
TMR2L_RUN
TMR2L
INT1 for TMR3
INT0
Capture
TMR2RL
TMR2H
TMR2RH
TMR2INTH
TMR2INTL
TMR2INTL_EN
TMR2SPLIT
TMR2H_CAP
TMR2L_CAP
TMR2H_RUN
TMR2L_RUN
Interrupt
Figure 33.3. Capture 16-bit Mode Block Diagram (Wide Mode)
33.4. 8-bit Timer/Timer Mode (Split Mode)
When TMR2SPLIT=1, the timer operates as two independent 8-bit timers. Each of the 8-bit timers can
independently operate in either 8-bit timer or 8-bit capture modes. The only common signals for both 8-bit
timers are capture event input signal and the interrupt output signal. Therefore, four possible configura-
tions are possible in split mode. All of them are described in the subsequent sections.
If TMR2L_CAP=0 and TMR2H_CAP=0, both halves operate as two independent 8-bit timers with indepen-
dently set clocks.
As the 8-bit timer register increments and overflows from 0xFF to 0x00, the 8-bit value in the time reload
registers (TMR2RH or TMR2RL) is loaded into the corresponding timer register (TMR2H or TMR2L), and
the corresponding byte overflow flag TMR2INTH or TMR2INTL are set, respectively. If timer interrupts are
enabled (see IE and EIE1 registers), an interrupt will be generated on each timer overflow.
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