RF60 Datasheet, PDF (126/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
30. Clock Output Generation
The device includes an option to be used as a clock generator for other chips connected to the device. The
generated clock frequency, clk_out, is derived from the internal 24MHz oscillator. System clock division
set in SYSGEN register has no effect on the clk_out frequency.
The clk_out is an output of a divider with programmable division from 1 to 31 in an increment of 1. There-
fore, the output frequency of the output clock can range from 24MHz to 24MHz/31 = 774kHz.
The divider has an option to keep the clk_out duty cycle to 1:1 even for odd division ratios. There is an
option of at which logic level the clk_out stops when the clock generator is disabled.
The clock divider/generator always finishes the period it started before it accepts a new division factor
CLKOUT_DIV. It is recommended to fix all the settings before enabling the output clock generator. The
master enable is PORT_CLKEN bit in the PORT_SET register.
CLKOUT_SET
Enable
24MHz
Clear
Divide by
CLKOUT_DIV[4:0]
Symmetry
1:1 Duty
Cycle
GPIO[6]
GPIO[4]
PORT_SET
Figure 30.1. Output Clock Generator Block Diagram
Tel: [phone]
Fax: [phone]
126
E-mail: [e-mail] http://www.hoperf.com