RF60 Datasheet, PDF (124/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
SFR Definition 29.7. PORT_SET
Bit
Name
Type
Reset
7
EDGE_
INT1
R/W
0
6
EDGE_
INT0
R/W
0
5
4
PORT_CLKOUT[1:0]
R/W
R/W
0
0
3
PORT_
CLKEN
R/W
0
2
PORT_
REFEN
R/W
0
1
0
RESERVED
R/W
R/W
0
0
SFR Address = 0xB6
Bit Name
Function
7 EDGE_ Edge control for INT1.
INT1 This bit controls whether single edge or both edges invoke the interrupt.
0 .. single edge, polarity specified by NEG_INT1 in PORT_INTCFG
1 .. both edges, which means any edge, invoke INT1 interrupt
6 EDGE_ Edge control for INT0.
INT0 This bit controls whether single edge or both edges invoke the interrupt.
0 .. single edge, polarity specified by NEG_INT0 in PORT_INTCFG
1 .. both edges, which means any edge, invoke INT0 interrupt
5:4 PORT_ Select what GPIO pin as clock output pin:
CLKOUT port_clkout[0] .. GPIO[4]: 1 .. clk output, 0 .. normal operation
[1:0] port_clkout[1] .. GPIO[6]: 1 .. clk output, 0 .. normal operation
Both outputs can be used simultaneously. The actual clock waveform can be
enabled/disabled by port_clken bit, but the GPIO configuration is purely controlled by
port_clkout.
3 PORT_ Enable output clock, which is possibly coming out on GPIO[4] and/or GPIO[6].
CLKEN This bit is just a clock enable/disable, it does not configure the GPIO for clock
outputs. The port configuration must be done by port_clkout below. The generated
clock division is controlled by CLKOUT_SET register. If the clock is disabled by
PORT_CLKEN=0 the current period in progress will be finished and the output clock
will stop as logic 0.
2 PORT_ Enable clk_ref reference clock to come from GPIO[3].
REFEN The GPIO[3] pad is forced to be an input. There is not need to change p0 or p0con
register values, since port_refen has higher priority.
1:0 RESERVED RESERVED.
These bits must be left at 0.
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