RF60 Datasheet, PDF (133/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
32.1. RTC Interrupt Flag Time Uniformity
Since 100us and 200us pulse duration is not exactly an integer multiple of the 24MHz/128 frequency, the
fractional division was used. The 100us and 200us pulse durations are uniform on average, when observed
over a sufficiently long timer period. Instantaneous time difference in between subsequent 100us and 200us
pulses is not 100us or 200us, respectively, but fluctuates around those two values.
100us pulse train .. the 100us pulse train consists of rtc_tick time duration of 19, 19, 19, 18 ticks. That
means that 3 subsequent 100us pulses has time difference of 19 * rtc_tick periods, which is 19 *
5.33us = 101.33us. That is followed by a singe duration or 18 * rtc_tick period duration, which is 18 *
5.33us = 96us. On average, the 100us pulse time period is (3 * 19 + 18)/4 * rtc_tick period, which is
18.75 * 5.33us = 100us exactly.
200us pulse train .. for 200us the pulse train consists of rtc_tick time duration of 38, 37 ticks. That
means that the pulse train is an alternation train of 38 * 5.33us = 202.66us and 37 * 5.33us = 197.33us,
when on average the duration is (38 + 37)/2 * 5.33us = 200us exactly.
The pulse trains for 400us pulses and longer have a uniform, exact, time periods.
32.2. Register Description
The RTC timer is controlled by the RTC_CTRL SFR register. If there is a need for precise beginning of the
RTC timer period, the internal tick generator can be cleared by writing a bit RTC_TICKCLR in the SYSGEN
register.
The rtc_tick generator runs freely whenever the RTC timer is enabled by RTC_ENA=1. If the user needs to
clear the RTC timer to synchronize it with some event, writing ‘1’ to RTC_CLR will clear the timer, which
keeps running. The RTC rtc_tick generator is not cleared by that event. Therefore, there will be up to
5.33us time uncertainty in the calculated time period. Clearing of the RTC rtc_tick generator is achieved by
writing ‘1’ into the RTC_TICKCLR bit in SYSGEN register.
To achieve exact synchronization it is recommended to write 1 into the RTC_TICKCLR, then 1 to
RTC_CLR, followed by another 1 into the RTC_TICKCLR. In assembly using the M_<field> masks 8-bit
mask notation from the supplied assembly include file:
orl SYSGEN, #M_RTC_TICKCLR
orl RTC_CTLR, #M_RTC_CLR
orl SYSGEN, #M_RTC_TICKCLR
The reason for splitting the clear is that the RTC tick output, rtc_tick can also be selected as a time source
for TMR2 and TMR3, so there is a need to have separate control over the rtc_tick generator clearing.
To get the RTC tick generator running the RTC_ENA=1 must be set. Therefore, even if the RTC interrupt is
not used, the RTC timer must be enabled if the user wants to use the rtc_tick as a clock source for TMR2 or
TMR3.
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