RF60 Datasheet, PDF (128/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
Bit Name
Function
7 CLKOUT_ CLKOUT Clear.
CLR Write 1 to this bit clears the generated clock divider. The generated clock output is
forced to 0. The pulse must be aligned with the registered write enable for this regis-
ter, therefore the generated clear pulse must be registered.
Reading this bit has CLKOUT_IDLE meaning. If read as 1 then it indicates that the
clock divider generator is idle. It can be used to wait for the clock to get idle after the
user clock output was disabled by PORT_SET.PORT_CLKEN=0. If this bit is read as
1 the clock division generator by factor 2 and above is running and the current user
clock period is still in progress.
The user could use this bit to synchronously switch the CLKOUT_DIV division factor,
but it is not necessary. The synchronous clock period switching is built in the hard-
ware. See the CLKOUT_DIV section above. To switch the clocks immediately without
waiting for the current period to end, write 1 to this bit. The write 1 to this bit can be
combined with setting the new CLKOUT_DIV value in this register at the same time.
6 CLKOUT_ CLKOUT Inversion.
INV Invert the generation clock. The invertor is at the very end of the clock generation
chain. Normally, if this bit is 0, if the generated clock is disabled the output is at 0. With
this bit set to 1 the output is inverted, therefore the generated clock stops at 1. This bit
must be set before customer clock is enabled to the port output by setting
PORT_SET.PORT_CLKEN=1. If changed later the clock inversion takes effect imme-
diately with possibility of short clock pulse being generated at the clock output.
5 CLKOUT_ CLKOUT Symmetry.
SYM If this bit set to 1 then the output clock duty cycle is very close to 1:1 irrespective of
the division factor. However, the generated clock waveform is a combination of
outputs of two flops and therefore might jitter more. If this bit is 0 then for odd division
factor there is a single 25MHz period difference in between halves of the generation
output clock.
This bit must be set before customer clock is enabled to the port output by setting
PORT_SET.PORT_CLKEN=1.
4:0 CLKOUT_ CLKOUT Division Factor.
DIV[4:0] Division factor of the 25 MHz oscillator clock for generation of the output customer
clock. The enable of the clock is controlled by the PORT_CLKEN and
PORT_CLKOUT bits in PORT_SET register. The division factors 0 and 1 pass the
25 MHz internal cheap oscillator output as output clocks. Value bigger than 1 is the
actual division factor of the 25 MHz.
If CLKOUT_SYM=0 (recommended), the generated clock is an output of a flop. For
odd division ratios the first part of the period in logic 0 is one 25 MHz clock cycle
shorter than the second high half part of the period of generated clock, assuming
CLKOUT_INV=0.
If the clock is disabled by PORT_CLKEN=0 the current period in progress will be
finished. To monitor when the output gets idle monitor the CLKOUT_CLR bit below.
The CLKOUT_DIV bit can be changed any time. The new setting will take effect only
after the current period finishes. For the new setting to take effect immediately see
CLKOUT_CLR.
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