RF60 Datasheet, PDF (55/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
SFR Definition 14.2. SYSGEN
Bit
7
6
5
4
Name ^SYSGEN_
SHUT-
DOWN
Type ^R/W
RE-
SERVED
R
PWR_1ST
_TIME
R
RTC_
TICKCLR
W
Reset
0
0
—
0
SFR Address = 0xBE
3
PORT_
HOLD
R/W
0
2
1
0
SYSGEN_DIV[2:0]
R/W
0
0
0
Bit Name
Function
7 SYSGEN_ _{System Generator Shutdown.}
SHUT-
DOWN
Setting this bit causes shutdown of MCU and most analog. Recovery from this is via
falling edge on any GPIO, which results in a power up and a power on reset. This is
THE bit that shuts down the power to nearly everything.
0: Normal operation
1: Shutdown
6 RESERVED _Reserved.
Read as 0. Write has no effect.
5 PWR_1ST_ _{Initial Powerup Indicator.}
TIME _{Read only register. It will get set when power up was caused by a battery insertion.}
4
RTC_ _{Real Time Clock Clear.}
TICKCLR _{0: Normal operation}
1: Clears the real time clock 5.12us counter.
3 PORT_ _{Port Hold.}
HOLD _{This bit needs to be set before shutting down, it delays any button pushes that occur}
between this bit setting and shutdown until the chip completes shutdown.
0: Normal operation
1: Holds GPIO port values until shutdown is complete
2:0 SYSGEN_ _{System Generator Divider.}
DIV[2:0] _{System clock divider control to generate the system clock.}
000: 24 MHz; div = 1
001: 12 MHz; div = 2
010: 6.0 MHz; div = 4
011: 3.0 MHz; div = 8
100: 1.5 MHz; div = 16
101: 0.75 MHz; div = 32
110: 0.375 MHz; div = 64
111: 0.1875 MHz; div = 128
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