RF60 Datasheet, PDF (57/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
16. Frequency Counter
The frequency counter allows the measurement of the ratio of two selected clock sources: a low frequency
clock which defines a counting interval, and a high frequency clock which is counted.
The frequency counter consists of an interval counter, driven by one of the six clock sources. Programming
of the interval counter determines how long the main counter will count one of the two high speed clocks,
LC oscillator or DIVIDER output.
FC_CTRL
New count trigger
GPIO[3]
GPIO[0]
LC_OSC
0
DIVIDER
1
Port
Controller
Xtal
Oscillator
3
Freq counter
disabled
0
clk_ref
1
clk_osc (24MHz)
clk_sys
clk_xo
2
clk_int
3
4
RESERVED
5
SLEEP TIMER
5
7
RESERVED
Interval
Counter
FC_INTERVAL
Long word 4 byte result count
read from XREG
FC_COUNT
(LWORD lFcCount)
FC_DONE
FC_BUSY
FC_DIV_SEL
Interrupt
FC_MODE
Figure 16.1. Frequency Counter Block Diagram
The block diagram of the frequency counter is in Figure 16.1. When the FC_MODE=0, the frequency coun-
ter is disabled. The only way to disable the frequency counter is to set the FC_MODE=0. The frequency
counter stops counting immediately, so it can be restarted by setting FC_MODE to some functional mode
immediately.
If the frequency counter is enabled by setting FC_MODE to other than the 0 value, it enters the idle state.
To start the counter, the interval counter has to be triggered by writing 1 to the FC_BUSY bit. By writing
FC_BUSY=1, the FC_DONE bit gets cleared as well. The user can also clear the FC_DONE bit in software
after reading the main FC_COUNT value.
Once the interval counter is triggered, and after several clk_sys cycles synchronization delay it waits for
the first rising edge of the clk_int clock, which is the output of the interval counter clock selector mux. It
then enables the main frequency counter FC_COUNT clock. After the interval counter counts the interval
specified by FC_INTERVAL SFR register, another rising edge of the clk_int stops the clocks to the main
FC_COUNT counter. The interval counter edge to edge counting and main FC_COUNT clock enable is
measured very accurately in between the clk_int rising edges.
When the interval counter is finished with the interval count, it clears the FC_BUSY=0 bit and after a few
cycles of clk_sys synchronization delay it sets the FC_DONE=1 bit. Both interval counter and main
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