RF60 Datasheet, PDF (134/157 Pages) –

RF60 CRYSTAL-LESS SOC TRANSMITTER v1.0
SFR Definition 32.1. RTC_CTRL
Bit
7
6
5
Name ^{RTC_INT RTC_ENA RTC_CLR}
Type ^R/W
R/W
W
Reset
0
0
0
4
3
RESERVED
R
R
0
0
2
1
0
RTC_DIV[2:0]
R/W
0
0
0
SFR Address = 0x9C
Bit Name
Function
7 RTC_INT Real Time Clock Interrupt Flag
Set after the time interval set by RTC_DIV field elapses. Software must clear the flag.
Hardware will not clear the flag
6 RTC_ENA _{Real Time Clock Enable}
If set to 1 then the RTC_TICK and bottom part of the pulse generator starts running
where it left off. If RTC_DIV >=3 then top half also starts.
0: RTC disabled
1: RTC enabled.
5 RTC_CLR _{Real Time Clock Clear}
Writing 1 will clear the pulse generator but will leave the RTC_TICK generator intact.
See the RTC_TICKCLR in the SYSGEN register for clearing the RTC_TICK counter.
0: Normal operation
1: RTC cleared
4:3 RESERVED _Reserved
Read as 0x00. Write has no effect.
2:0 RTC_DIV Real Time Clock Divider
[2:0] _{Select the divider of the RTC_TICK to determine the interval for the RTC interrupt}
generation.
000: No interrupt generation
001: 100us .. it is a 19/19/19/18 divider
010: 200us .. it is a 38/37 divider
011: 400us
100: 800us
101: 1ms
110: 2ms
111: 5ms
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